1. Technical Field
Some embodiments of the inventions relate to memory devices that reflect back error detection signals such as cyclic redundancy check (CRC) checksums.
2. Background Art
Various arrangements for memory devices in a memory system have been proposed. For example, in a traditional synchronous dynamic random access memory (DRAM) system, memory devices communicate data through bidirectional data buses and receive commands and addresses through command and addresses buses. In some implementations, the memory devices have stubs that connect to the buses in a multi-drop configuration. Other designs include point-to-point signaling. Bidirectional signaling may be sequential or simultaneous.
Various error detection techniques have been used. Cyclic redundancy check (CRC) is a well know procedure wherein a checksum is produced from a large number of bits. The checksum is used to detect errors after transmission or storage. The checksum is calculated and appended to data before transmission or storage. The checksum of the data is recalculated later and compared with the appended checksum. If the original and later calculated checksums do not match, there is reason to doubt the accuracy of the data or a command contained in the data. Various responses can be made such as resending the data. There are a variety of types of CRC procedures and recovery methods. Some of the error detection techniques, such as error correcting code (ECC), involve error correction techniques.
As speeds of interconnect signaling increase, the bit error rate (BER) may also increase. CRC procedures have been are proposed for use in memory systems including DRAM memory systems. The checksums can be recalculated in the DRAM and compared with the received checksum. Write data can stay in a posted write buffer until a match is determined. The system can respond in various ways if there is not a match including ignoring certain data, resending certain data, including chains of commands, perform ECC, reinitializing a link, and/or reinitializing a portion of a memory core.
Improving error coverage on write data to a DRAM memory device could be accomplished with stronger CRC codes and a significant amount on logic in the DRAM memory device to generate CRC.
Memory controllers provide various commands to memory devices. These commands include a precharge command (PRE), an activate command (ACT), a read command (RD), and a write command (WR). Some commands come in chains over time in which some commands follow other commands in a progression (for example, PRE, ACT, CAS). Read and write commands are sometimes called CAS commands. There are many variations on these commands. Some compound commands from memory controllers are divided into sub-commands by the memory device. For example, a combined ACT/RD command, is divided into an ACT command and a RD command by the memory device.
Commands, addresses, write data, and read data have been transmitted in a variety of forms including packets and frames. Frames are a type of packet in which signals on parallel lanes are provided in a particular number of unit intervals (UI).
Memory modules include a substrate on which a number of memory devices are placed. A dual in-line memory module (DIMM) is an example. In some systems, a buffer is also placed on the substrate. For at least some signals, the buffer interfaces between the memory controller (or another buffer) and the memory devices on the module. In such a buffered system, the memory controller can use different signaling with the buffer than the buffer uses with the memory devices. Multiple modules may be in series and/or parallel. There may be one memory device in a chip or more than one memory device in a chip. Chips may be in stacks.
Some computer systems having included some memory devices on a motherboard and other memory devices on a memory module or other card in a connector on the motherboard.
In some memory systems, the memory devices receive signals and repeat them to other memory devices as well as provide requested data signals to next memory devices. Read data signals can be provided to the memory controller through a point-to-point unidirectional return link from the last memory device in a series of memory devices in a looped fashion or from a memory device that is not the last memory device in the series.
Memory controllers have been used in chipset hubs and in a chip that includes a processor core. Some computer systems include wireless transmitter and receiver circuits.